The online training programme titled “Comprehensive VHDL Design: VLSI Digital Design for FPGA,” offered by the University Semiconductors Competence Centre, will be held on 23–26 March 2026.
The training will be entirely online, taking place each day from 09:00 to 16:00 (CET), and will be delivered in English. Participation is free of charge; however, the number of available slots is limited.
This four-day course is designed for both beginners in digital design and experienced designers who wish to learn VHDL for FPGA development. By the end of the training, participants are expected to be able to write synthesizable VHDL code, understand how it maps to hardware, verify designs through testbenches, and identify design errors at an early stage using industry-standard tools.
On the first day of the programme, VHDL fundamentals and hierarchical design will be covered; the second day will focus on synthesis processes, finite state machines, and parametrized design. During the third and fourth days, participants will take part in hands-on sessions, developing various VHDL applications using the Questa simulation software developed by Siemens.
Further details and registration are available at the following link:
https://www.um.edu.mt/uscc/upskillingcourses/comprehensivevhdldesigncourse/
Click here to access the training announcement.